DS1012 2-in-1 sub-miniature silicon delay line with logic DS1012 021798 1/7 features ? all-silicon time delay ? 53 m w max. cmos quiescent mode ? surface mount 8-pin mini-soic and standard 8-pin dip ? 2 independent buffered delays per input ? option of complemented output(s) ? option of timed and, nand, or, nor, xor, xnor, half-xor and half-xnor logic outputs ? delay tolerance: 1.5 ns (delays: 3-10 ns), 2.0 ns (delays: 11-40 ns) ? vapor phase, ir and wave solderability ? economical ? ttl/cmos-compatible ? quick turn prototypes ? custom delays and logic options available pin assignment 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 gnd out1 out3 in1 v cc out2 in2 out4 gnd out1 out3 in1 v cc out2 in2 out4 DS1012m 8-pin dip (300 mil) see mech. drawings section DS1012z 8-pin soic (150 mil) see mech. drawings section pin description in1, in2 inputs out1, out2 outputs (delays) out3, out4 outputs (delays, logic) gnd ground v cc +5 volts description in its most simple configuration, the DS1012 2-in-1 sub-miniature silicon delay line chip provides two in- puts, each of which in turn provides independent delays to a pair of outputs. the DS1012-1 and DS1012-3 are examples of catalog parts having this basic configura- tion. any of the four outputs can be inverted at the time of manufacture. for applications requiring two-input timed logic func- tions, at the time of manufacture the simple delay on out4 can be replaced by one of the following: or, nor, xor, or xnor. similarly, a timed and, nand, half-xor (d3 and d4 ), or not half-xor (d3 or d4) can be substituted for the simple delay on out3. DS1012-2, DS1012-4, and DS1012-5 are examples of catalog parts configured with logic functions on out3 and out4. note that DS1012-2 also utilizes an output inversion on out2. in any configuration, delays d1 (t d1 ) and d2 (t d2 ) can be specified within the range of ~3 ns to 10 ns. delays d3 (t d3 ) and d4 (t d4 ) can be specified to have values be- tween ~3 ns and 40 ns. the worst case leading edge delay accuracy at nominal voltage and room tempera- ture is 2 ns. the DS1012 is offered in two packages: an 8-pin dip and an 8-pin 150 mil wide mini-soic. dallas semiconductor offers the DS1012 in a wide vari- ety of custom delay and logic configurations. for special requests and quick turn delivery, call (972) 3714348.
DS1012 021798 2/7 logic diagram figure 1 in1 in2 delay d1 delay d3 delay d4 delay d2 function f3 function f4 out1 out3 out4 out2 function f3 can be one of the following: d3 d3 and d4 d3 half-xor d4 d3 d3 nand d4 d3 half-xnor d4 function f4 can be one of the following: d4 d3 or d4 d3 xor d4 d4 d3 nor d4 d3 xnor d4 note: any output(s) can be inverted at time of manufacture. if d1 > 10 ns, d1 = d3. if d2 > 10 ns, d2 = d4.
DS1012 021798 3/7 part number delay and configuration table 1 catalog p/n t d1 (ns) t d2 (ns) t d3 (ns) t d4 (ns) out1 out2 out3 out4 DS1012-1 5 5 10 10 d1 d2 d3 d4 DS1012-2 5 5 10 10 d1 d2 d3.d4 d3+d4 DS1012-3 3 7 10 40 d1 d2 d3 d4 DS1012-4 5 5 25 25 d1 d2 d3hxd4 d3xd4 DS1012-5 10 10 5 5 d1 d2 d3.d4 d3+d4 DS1012-7 15 4 4 14 d1 d2 d3 d3xd4 DS10129 5 25 5 25 d1 d2 d3hxd4 d3xd4 DS1012-d16 4 19.6 4 19.6 d1 d2 d3.d4 d3xd4 DS1012-d20 4 16.5 4 16.5 d1 d2 d3.d4 d3xd4 DS1012-d25 4 14 4 14 d1 d2 d3.d4 d3xd4 DS1012-d33 4 11.5 4 11.5 d1 d2 d3.d4 d3xd4 DS1012-d50 4 9 4 9 d1 d2 d3.d4 d3xd4 DS1012-v20 25 50 25 50 d1 d2 d3.d4 d3+d4 DS1012-v40 12.5 25 12.5 25 d1 d2 d3.d4 d3xd4 DS1012-v50 10 20 10 20 d1 d2 d3.d4 d3xd4 DS1012-v60 8.3 8.3 8.3 8.3 d1 d2 d3.d4 d3+d4 note: . = and, + = or, x = xor, hx = halfxor contact dallas semiconductor for information on custom configurations and timing delays. test circuit figure 2 pulse +5v +5v time vhf device 74f04 stop tip start tip (time interval probe) z 0 = 50 w z 0 = 50 w vhf switch control unit generator interval counter switch control unit under test
DS1012 021798 4/7 test setup description figure 2 illustrates the hardware configuration used for measuring the timing parameters on the DS1012. the input waveform is produced by a precision pulse gener- ator under software control connected to the inputs by vhf switch control units. time delays are measured by a time interval counter (20 ps resolution) connected be- tween the inputs and the outputs. outputs are con- nected to the counter by a vhf switch control unit. all measurements are fully automated, with each instru- ment controlled by a central computer over an ieee 488 bus. test conditions input: ambient temperature: 25 c 3 c supply voltage (v cc ): 5.0v 0.1v input pulse: high = 3.0v 0.1v low = 0.0v 0.1v source impedance: 50 ohms max. rise and fall time: 3.0 ns max. pulse width: 50 ns period: 100 ns output: each output is loaded with a 74f04. delay is measured between the 1.5v level of the rising edge of the input sig- nal and the 1.5v level of the corresponding edge of the output. note: these conditions are for test only and do not restrict the operation of the device un- der other data sheet conditions.
DS1012 021798 5/7 absolute maximum ratings* voltage on any pin relative to ground -1.0v to +7.0v operating temperature 0 c to 70 c storage temperature -55 c to +125 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (0 c to 70 c; v cc = 5.0v 5%) parameter symbol test min typ max units notes supply voltage v cc 4.75 5.00 5.25 v 1 high level input voltage v ih 2.2 v cc +0.5 v 1 low level input voltage v il -0.5 0.8 v 1 input leakage current i i 0.0v < v i < v cc -1.0 1.0 m a active current i cc1 v cc = max; period = min 40.0 70.0 ma 2 quiescent current i cc2 v cc = max. 10 m a 5 high level output current i oh v cc = min v oh = 2.4v -1.0 ma low level output current i ol v cc = min. v ol = 0.5v 8.0 ma ac electrical characteristics (t a = 25 c; v cc = 5v 5% ) parameter symbol min typ max units notes input pulse width t wi ns 6 input to output (leading edge) t d1 , t d2 , t d3 , t d4 ns 3, 4 power-up time t pu 0 ns 7 period 2(t wi ) ns capacitance (t a = 25 c) parameter symbol min typ max units notes input capacitance c in 5 10 pf
DS1012 021798 6/7 delay function figure 3 period t wi t wi t d1 ~t d1 t d2 t d2 t d3 ~t d3 t d4 ~t d4 in1 in2 out1 out2 out3 ainverto out4 ainverto logic functions figure 4 period t wi t wi t d4 ~t d3 t d3 t d3 t d3 t d4 t d4 ~t d3 ~t d4 ~t d4 in1 in2 out3 aando out4 aoro out3 ahxoro out4 axoro t d3 < t d4
DS1012 021798 7/7 notes: 1. all voltages are referenced to ground. 2. measured with outputs open, minimum period. i cc1 (max.) for any value of period can be calculated using the formula: i cc1 (max.) = 840/period + i cc2 where i cc1 , i cc2 in ma, period in ns example: if period = 50 ns then i cc1 (max) = 840/50 + 0.01 = 16.81 ma 3. v cc = 5v @ 25 c. delays referenced to leading (input rising) edges are accurate within 1.5 ns for values between 3 to 10 ns and 2 ns for values between 11 to 40 ns. delays referenced to trailing (input falling) edges will typically equal the corresponding leading edge delay within 1 ns. 4. see the section entitled atest conditions.o 5. for the quiescent mode, both inputs must meet the conditions 0.3v > v i or vi > v cc - 0.3 6. for specified accuracy, t wi (min) is the longer of 3(t d1 ), 3(t d2 ), 3(t d3 ), or 3(t d4 ). pulse doublers designed for single frequency use will meet specified accuracies at 50% duty cycle; i.e., 2(t wi ) = 1/freq = period. cus- toms will be adjusted to be accurate at customer input width specifications when t wi is longer than t d1 , t d2 , t d3 , and t d4 . 7. on power-up, the DS1012 will supply timing and logic functions with specified accuracy as soon as v cc achieves nominal value.
|
